Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

15.3. SD/MMC Controller Signal Description

The following table shows the SD/MMC controller signals that are routed to the FPGA and the HPS I/O.
Note: The last five signals in the table are not routed to HPS I/O, but only to the FPGA.
Table 124.  SD/MMC Controller Interface I/O Pins

Signal

Width

Direction

Description

sdmmc_cclk_out

1

Out

Clock from controller to the card

sdmmc_cmd_i

1

In

Card command

sdmmc_cmd_o 1 Out
sdmmc_cmd_oe   Out
sdmmc_pwr_ena_o

1

Out

External device power enable

sdmmc_data_i

8

In

Card data

sdmmc_data_o 8 Out
sdmmc_data_oe 1 Out
sdmmc_cdn_i 1 In Card detect signal
sdmmc_wp_i 1 In Card write protect signal
sdmmc_vs_o 1 Out Voltage switching between 3.3V and 1.8V
sdmmc_rstn_o 1 Out Card reset signal used in MMC mode
sdmmc_card_intn_i 1 In Card interrupt signal