Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

8.3.12. FIFO Buffers and Clock Crossing

The interconnect provides FIFO buffers in the following locations:

  • On interfaces to all HPS master and slaves except onchip RAM and boot ROM
  • Between subswitches

In addition to buffering, these FIFOs also provide clock domain crossing where masters and slaves operate at a different clock frequency from the switch they connect to.