Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.1. Features of the Clock Manager

The Clock Manager offers the following features:

  • Generates and manages clocks in the HPS
  • Contains the following PLL clock groups:
    • PLL 0 (Main)—contains clocks for the Arm* Cortex®-A9 microprocessor unit (MPU) subsystem, level 3 (L3) interconnect, level 4 (L4) peripheral bus, and debug
    • PLL 1 (Peripheral)—contains clocks for PLL-driven peripherals
    • SDRAM—contains clocks for the SDRAM subsystem
  • Allows scaling of the MPU subsystem clocks without disabling peripheral and SDRAM clock groups
  • Generates clock gate controls for enabling and disabling most clocks
  • Initializes and sequences clocks for the following events:
    • Cold reset
    • Safe mode request from reset manager on warm reset
  • Allows software to program clock characteristics, such as the following items discussed later in this chapter:
    • Input clock source for SDRAM and peripheral PLLs
    • Multiplier range, divider range, and six post-scale counters for each PLL
    • Output phases for SDRAM PLL outputs
    • VCO enable for each PLL
    • Bypass modes for each PLL
    • Gate off individual clocks in all PLL clock groups
    • Clear loss of lock status for each PLL
    • Safe mode for hardware-managed clocks
    • General-purpose I/O (GPIO) debounce clock divide
  • Allows software to observe the status of all writable registers
  • Supports interrupting the MPU subsystem on PLL‑lock and loss‑of‑lock
  • Supports clock gating at the signal level

The clock manager is not responsible for the following functional behaviors:

  • Selection or management of the clocks for the FPGA-to-HPS and HPS-to-FPGA interfaces. The FPGA logic designer is responsible for selecting and managing these clocks.
  • Software must not program the clock manager with illegal values. If it does, the behavior of the clock manager is undefined and could stop the operation of the HPS. The only guaranteed means for recovery from an illegal clock setting is a cold reset.
  • When re-programming clock settings, there are no automatic glitch-free clock transitions. Software must follow a specific sequence to ensure glitch-free clock transitions. Refer to Hardware-Managed and Software-Managed Clocks section of this chapter.