Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

2.2.6.1. NAND Flash Controller

The NAND flash controller is based on the Cadence® Design IP® NAND Flash Memory Controller and offers the following functionality and features:

  • Supports one x8 NAND flash device
  • Supports Open NAND Flash Interface (ONFI) 1.0
  • Supports NAND flash memories from Hynix, Samsung, Toshiba, Micron, and ST Micro
  • Supports programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction) ECC sector size
  • Supports pipeline read-ahead and write commands for enhanced read/write throughput
  • Supports devices with 32, 64, 128, 256, 384, or 512 pages per block
  • Supports multiplane devices
  • Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB
  • Supports single-level cell (SLC) and multi-level cell (MLC) devices with programmable correction capabilities
  • Provides internal DMA
  • Provides programmable access timing