Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

19.4.1.5. SPRAM

An SPRAM implements the data FIFO buffers for host and device modes. The size of the FIFO buffers can be programmed dynamically.

The SPRAM supports ECCs. ECCs can be enabled through the system manager, by setting the RAM ECC Enable (en) bit in the USB0 or USB1 RAM ECC Enable Register (usb0 or usb1), in the ECC Management Register Group (eccgrp). Single‑bit and double‑bit errors in each USB instance can be injected using this register.

The SPRAM provides outputs to notify the system manager when single‑bit correctable errors are detected (and corrected), and when double‑bit (uncorrectable) errors are detected. The system manager generates an interrupt to the GIC when an ECC error is detected.