Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.4.2.7. Memory Region Remap

The ACP ID mapper has 1 GB of address space, which is by default a view into the bottom 1 GB of SDRAM. The mapper also allows transactions to be routed to different 1 GB‑sized memory regions, called pages, in both dynamic and fixed modes. The two most significant bits of incoming 32‑bit AXI address signals are replaced with the 2‑bit user‑configured address page decode information. The page decoder uses the values shown in Table 64.

Table 64.  Page Decoder Values

Page

Address Range

0

0x00000000—0x3FFFFFFF

1

0x40000000—0x7FFFFFFF

2

0x80000000—0xBFFFFFFF

3

0xC0000000—0xFFFFFFFF

With this page decode information, a master can read or write to any 1 GB region of the 4 GB memory space while maintaining cache coherency with the MPU subsystem.

Using this feature, a debugger can have a coherent view into main memory, without having to stop the processor. For example, at reset the DAP input ID (0x001) is mapped to output ID 2, so the debugger can vary the 1 GB window that the DAP accesses without affecting any other traffic flow to the ACP.