Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

8.2.2. System Interconnect Architecture

The L3 interconnect is a partially-connected switch fabric. Not all masters can access all slaves.

Internally, the L3 interconnect is partitioned into the following subswitches:

  • L3 interconnect
    • Interconnect used to transfer high-throughput 64-bit data
    • Operates at up to half the MPU main clock frequency
    • Provides masters with low-latency connectivity to AXI bridges, on-chip memories, SDRAM, and FPGA manager
  • L3 master peripheral switch
    • Used to connect memory-mastering peripherals to the interconnect
    • 32-bit data width
    • Operates at up to half the interconnect clock frequency
  • L3 slave peripheral switch
    • Used to provide access to level 3 and 4 slave interfaces for masters of the master peripheral and interconnects
    • 32-bit data width
    • Five independent L4 buses

The L3 master and slave peripheral switches are fully-connected crossbars. The L3 interconnect is a partially-connected crossbar. The following table shows the connectivity matrix of all the master and slave interfaces of the L3 interconnect.