Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

28.2.5. Peripheral FPGA Clocks

The HPS peripheral clocks are exposed when the peripheral signals are routed to the FPGA.

Table 226.  Peripheral FPGA Clocks

Clock Name

Description

emac_md_clk

Ethernet PHY management interface clock

emac_gtx_clk

Ethernet transmit clock that is used by the PHY in GMII mode

emac_rx_clk_in

Ethernet MAC reference clock from the PHY

emac_tx_clk_in

Ethernet MAC uses this clock input for TX reference

emac_ptp_ref_clock

Ethernet timestamp precision time protocol (PTP) reference clock

qspi_sclk_out

QSPI master clock output

spim_sclk_out

SPI master serial clock output

spis_sclk_in

SPI slave serial clock input

i2c_clk

I2C outgoing clock (part of the SCL bidirectional pin signals)

i2c_scl_in

I2C incoming clock (part of the SCL bidirectional pin signals)