Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.3.1.1. PLLs

The clock manager contains three PLLs: PLL 0 (main), PLL 1 (peripherals), and SDRAM. These PLLs generate the majority of clocks in the HPS. There is no phase control between the clocks generated by the three PLLs.

Each PLL has the following features:

  • Phase detector and output lock signal generation
  • Registers to set VCO frequency
    • (M) Multiplier range is 1 to 4096
    • (N) Divider range is 1 to 64
  • Six post-scale counters (C0-C5) with a range of 1 to 512
  • PLL can be enabled to bypass all outputs to the osc1_clk clock for glitch-free transitions

The SDRAM PLL has the following additional feature:

  • Phase shift of 1/8 per step
    • Phase shift range is 0 to 7