Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

18.4.2. Timestamp Interface

The timestamp clock reference can come from either the Clock Manager or the FPGA fabric. If the FPGA has implemented the serial capturing of the timestamp interface, then the FPGA must provide the PTP clock reference.

In addition to providing a timestamp clock reference, the FPGA can monitor the pulse-per-second output from each EMAC module and trigger a snapshot from each auxiliary time stamp timer.

The following table lists the EMAC to FPGA IEEE1588 Timestamp Interface signals to and from each EMAC module.

Table 167.  EMAC to FPGA IEEE 1588 Timestamp Interface Signals

Signal Name

In/Out

Width

Description

f2h_emac_ptp_ref_clk

Timestamp PTP Clock reference from the FPGA

In

1

Used as PTP Clock reference for each EMAC when the FPGA has implemented Timestamp capture interface. Common for both EMACs.

ptp_pps_o

Pulse Per Second Output

Out

1

This signal is asserted based on the PPS mode selected in the Register 459 (PPS Control Register). Otherwise, this pulse signal is asserted every time the seconds counter is incremented. This signal is synchronous to f2h_emac_ptp_ref_clk and may only be sampled if the FPGA clock is used as timestamp reference.

ptp_aux_ts_trig_i

Auxiliary Timestamp Trigger

In

1

This signal is asserted to take an auxiliary snapshot of the time.

The rising edge of this internal signal is used to trigger the auxiliary snapshot. The signal is synchronized internally with clk_ptp_ref_i which results in an additional delay of 3 cycles. This input is asynchronous input and its assertion period must be greater than 2 PTP active clocks to be sampled.