Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

18.1.3. Management Interface

  • 32‑bit host interface to CSR set
  • Comprehensive status reporting for normal operation and transfers with errors
  • Configurable interrupt options for different operational conditions
  • Per-frame transmit/receive complete interrupt control
  • Separate status returned for transmission and reception packets