Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

5.3.7. Clock

The FPGA manager has two clock input signals which are asynchronous to each other. The clock manager generates these two clocks:

  • cfg_clk—the configuration slave interface clock input and also the DCLK output reference for FPGA configuration. Enable this clock in the clock manager only when configuration is active or when the configuration slave interface needs to respond to master requests.
  • l4_mp_clk—the register slave interface clock.