Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

2.2.7.7. DMA Controller

The DMA controller provides high-bandwidth data transfers for modules without integrated DMA controllers. The DMA controller is based on the Arm* Corelink* DMA Controller (DMA‑330) and offers the following features:

  • Micro-coded to support flexible transfer types
    • Memory-to-memory
    • Memory-to-peripheral
    • Peripheral-to-memory
    • Scatter-gather
  • Supports up to eight channels
  • Supports flow control with 31 peripheral handshake interfaces
  • Software can schedule up to 16 outstanding read and 16 outstanding write instructions
  • Supports nine interrupt lines: one for DMA thread abort and eight for external events