Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.3.14.1. Functional Description

The SCU is used to connect the Cortex®-A9 processors and the ACP to the L2 cache controller. The SCU performs the following functions:

  • When the processors are set to SMP mode, the SCU maintains data cache coherency between the processors.
    Note: The SCU does not maintain coherency of the instruction caches.
  • Initiates L2 cache memory accesses
  • Arbitrates between processors requesting L2 access
  • Manages ACP access with cache coherency capabilities.